Of course you have 3 gigs but when you bought the memory did you look at the cas latence and the mem timings. There are several limits on DRAM performance. Most noted is the read cycle time, the time between successive read operations to an open row. This time decreased from 10 ns for 100 MHz SDRAM to 5 ns for DDR-400, but has remained relatively unchanged through DDR2-800 and DDR3-1600 generations. However, by operating the interface circuitry at increasingly higher multiples of the fundamental read rate, the achievable bandwidth has increased rapidly.
Another limit is the CAS latency, the time between supplying a column address and receiving the corresponding data. Again, this has remained relatively constant at 10–15 ns through the last few generations of DDR SDRAM.
In operation, CAS latency is a specific number of clock cycles programmed into the SDRAM's mode register and expected by the DRAM controller. Any value may be programmed, but the SDRAM will not operate correctly if it is too low. At higher clock rates, the useful CAS latency in clock cycles naturally increases. 10–15 ns is 2–3 cycles (CL2–3) of the 200 MHz clock of DDR-400 SDRAM, CL4-6 for DDR2-800, and CL8-12 for DDR3-1600. Slower clock cycles will naturally allow lower numbers of CAS latency cycles.
SDRAM modules have their own timing specifications, which may be slower than those of the chips on the module. When 100 MHz SDRAM chips first appeared, some manufacturers sold "100 MHz" modules that could not reliably operate at that clock rate. In response, Intel published the PC100 standard, which outlines requirements and guidelines for producing a memory module that can operate reliably at 100 MHz. This standard was widely influential, and the term "PC100" quickly became a common identifier for 100 MHz SDRAM modules, and modules are now commonly designated with "PC"-prefixed numbers (PC66, PC100 or PC133 - although the actual meaning of the numbers has changed).A brief and simple version is Memory timings (or RAM timings) refer collectively to a set of four numerical parameters called CL, tRCD, tRP, and tRAS, commonly represented as a series of four numbers separated with dashes, in that respective order (e.g. 5-5-5-15). However, it is not unusual for tRAS to be omitted, or for a fifth value, the Command rate, to be added on. It also remains a common practice to advertise only CL. These parameters define, in clock cycles, the various forms of latency (responsiveness to random requests) that affect fundamental performance metrics of random access memory. Lower ("tight") timings imply better performance.
Modern DIMMs include a Serial Presence Detect (SPD) RAM that contains recommended memory timings for automatic configuration. The BIOS on a PC may allow the user to make adjustments in an effort to increase performance (with possible risk of decreased stability) or, in some cases, to increase stability (by lowering performance).
Memory timings are distinct from memory bandwidth; the latter measures the throughput of memory. It is possible for an advance in memory technology to increase both bandwidth (an apparent performance improvement) and latency (an apparent performance degradation). For example, DDR memory has been superseded by DDR2, and yet DDR2 has significantly higher latency at the same clock frequencies. However, DDR2 can be clocked faster, decreasing its cycle time; DDR2 clocked significantly higher than DDR also has lower latency (in nanoseconds) than DDR.
Name Symbol Definition
CAS latency CL The time between sending a column address to the memory and the beginning of the data in response. This is the time it takes to read the first bit of memory from a DRAM with the correct row already open.
Row Address to Column Address Delay TRCD The number of clock cycles required between the opening a row of memory and accessing columns within it. The time to read the first bit of memory from a DRAM without an active row is TRCD + CL.
Row Precharge Time TRP The number of clock cycles required between the issuing of the precharge command and opening the next row. The time to read the first bit of memory from a DRAM with the wrong row open is TRP + TRCD + CL.
Row Active Time TRAS The number of clock cycles required between a bank active command and issuing the precharge command. This is the time needed to internally refresh the row, and overlaps with TRCD. Typically approximately equal to the sum of the previous three numbers.
Notes:
RAS : Row Access Strobe
CAS : Column Access Strobe
TWR : Write Recovery Time, the time that must elapse between the last write command to a row and precharging it. Generally, TRAS = TRCD + TWR.
TRC : Row Cycle Time. TRC = TRAS + TRP.
All these timings will affect performance and with ram timings IT IS ALWAYS lower the better
Hey go to the ram manufactuers web site and find the optimal settings that you can change in the bios and if you can uninstall any unneeded programs